Non-volatile memory device for 2-bit operation and method of fabricating the same

ABSTRACT

A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

CROSS-REFERENCE TO RELATED PATENT APPLICATION

This application is a continuation application of U.S. patentapplication Ser. No. 12/692,197, filed on Jan. 22, 2010, which is acontinuation application of U.S. patent application Ser. No. 11/376,518,filed on Mar. 15, 2006, now U.S. Pat. No. 7,675,105, which claims thebenefit of Korean patent application number 10-2005-0023649, filed onMar. 22, 2005, in the Korean Intellectual Property Office, the contentsof which applications are incorporated herein in their entirety byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device, and moreparticularly, to a non-volatile memory device including a memory cellarray for 2-bit operation and a method of fabricating the same.

2. Description of the Related Art

A significant increase in memory density of non-volatile memory devicesor flash memory devices is needed. Therefore, there have been efforts toreduce the size of the memory cell. There have also been introducedmethods of increasing the memory density by increasing the number ofstates that can be stored in the memory cell. For example, a method ofrealizing 2-bit operation in one memory transistor structure isproposed.

FIG. 1 is a sectional view schematically illustrating a conventionalnon-volatile memory transistor device.

Referring to FIG. 1, a memory cell of the conventional non-volatilememory transistor device typically employs a transistor structure, whichincludes two source/drain regions 41, 45 in a semiconductor substrate10, a channel 11 disposed in the substrate between the firstsource/drain region 41 and the second source/drain region 45, and a gate30 formed on the channel 11. Further, a charge storage layer 20 may beinterposed between the gate 30 and the semiconductor substrate 10.

It is reported that 2-bit operation is possible in the transistorstructure as described above. For example, portions of the chargestorage layer 20 respectively disposed close to the first and secondsource/drain regions 41, 45 are defined as local first and second chargestorage regions 21, 23 respectively, or a storage node to realize 2-bitoperation.

In order to realize 2-bit operation in such a transistor structure,first and second bit lines BL1, BL2 must be independently connected tothe first and second source/drain regions 41, 45 respectively, and aword line WL must be connected to the gate 30. However, it has beenunderstood that it is very difficult to realize an interconnectionstructure, in which three discrete terminals, that is, WL, BL1, BL2, areindependently connected in one memory cell transistor as above.

In order to realize high integration of a memory device, several memorycells are connected to one word line WL, one bit line BL1, and one bitline BL2, and discrete memory cells must be aligned sufficiently toperform a write and/or a read operation independently. Since the bitlines BL1 and BL2 must be connected to one memory cell independently,the array of the word line WL, and the bit lines BL1 and BL2 must beconsidered very carefully.

If the gate 30 used for the word line WL extends along the directionthat the active region extends, that is, the direction that the activeregion extends from the first source/drain region 41 to the secondsource/drain region 45, it is difficult that the bit lines BL1 and BL2are directly connected to the first and second source/drain regions 41,45 since the gate 30 and the charge storage layer 20 extend on the firstand second source/drain regions 41, 45. Therefore, efforts have beenmade to design arrays of WL and BL1, BL2 for connecting memory cells for2-bit operation.

For example, in order to realize the array structure, there has beenproposed a structure extending in a direction where source/drain regions41, 45 cross with WL, for example, a buried bit line structure. Further,there has been also proposed a structure in which a gate 30 does notextend to other neighboring memory cells and is cut, and an additionalWL is connected to a discrete gate in each memory cell.

As shown in FIG. 1, if the gate 30 extends to a direction where anactive region extends, that is, from a first source/drain region 41 to asecond source/drain region 45, a charge storage layer 20 below the gate30 extends together with the gate 30. In this case, the charge storagelayer 20 necessarily extends to the isolation region for isolatingmemory cells.

The case considers convenience of processes, but may cause influencesbetween signals of the storage charges between cells connected to oneWL. Specifically, in the case that an integration density of a devicefor a highly-integrated memory device is increased, the mutualinfluence, for example, cross-talking phenomenon may be more serious.The stored charges, that is, interference between signals may functionas a factor to limit the increase of integration degrees of a device.Thus, it is required to develop a process technology being capable oflocally confining the charge storage layer 20.

SUMMARY OF THE INVENTION

The present invention provides a non-volatile memory device includingarrays of a word line, a first bit line, a second bit line, and anactive region to operate non-volatile memory cells for 2-bit operation,and a method of fabricating the same.

According to a first aspect, the invention is directed to a non-volatilememory device for 2-bit operation comprising: an active region and agate extending in a word line direction on a semiconductor substrate,and crossing each other repeatedly; a charge storage layer disposedbelow the gate, and confined at a portion where the gate and the activeregion cross; a charge blocking layer formed at an interface between thecharge storage layer and the gate; a tunnel dielectric layer formed atan interface between the charge storage layer and the active region;first and second source/drain regions formed at an exposed portion outof both sides of the gate in the active region; and first and second bitlines connected to the first and second source/drain regionsrespectively, and formed to extend in a bit line direction crossing theword line direction.

According to another aspect, the invention is directed to a non-volatilememory device for 2-bit operation comprising: active regions formed in afirst zigzag pattern to extend in a word line direction in asemiconductor substrate, and partially to be bent repeatedly; gatesformed in a second zigzag pattern to extend in a word line direction inthe semiconductor substrate, partially to cross with the active regions,and to be bent repeatedly in symmetry with the first zigzag pattern; acharge storage layer disposed below the gate, and confined at a portionwhere the gate and the active regions cross; a charge blocking layerformed at an interface between the charge storage layer and the gate; atunnel dielectric layer formed at an interface between the chargestorage layer and the active regions; first and second source/drainregions formed at an exposed portion out of both sides of the gate inthe active regions; and first and second bit lines connected to thefirst and second source/drain regions respectively, and formed to extendin a bit line direction crossing the word line direction.

According to another aspect, the invention is directed to a non-volatilememory device for 2-bit operation comprising: active regions formed in azigzag pattern and formed to extend in a word line direction in asemiconductor substrate and partially to be bent repeatedly; gatesformed in a straight pattern and formed to extend in a word linedirection on the semiconductor substrate and partially to cross theactive regions repeatedly; a charge storage layer disposed below thegate, and confined at a portion where the gate and the active regionscross; a charge blocking layer formed at an interface between the chargestorage layer and the gate; a tunnel dielectric layer formed at aninterface between the charge storage layer and the active regions; firstand second source/drain regions formed at an exposed portion out of bothsides of the gate in the active regions; and first and second bit linesconnected to the first and second source/drain regions respectively, andformed to extend in a bit line direction crossing the word linedirection.

According to another aspect, the invention is directed to a non-volatilememory device for 2-bit operation comprising: active regions formed in astraight pattern and formed to extend in a word line direction in asemiconductor substrate; gates formed in a zigzag pattern and formed toextend in a word line direction on the semiconductor substrate andpartially to cross the active regions repeatedly, and to be bentrepeatedly; a charge storage layer disposed below the gate, and confinedat a portion where the gate and the active regions cross; a chargeblocking layer formed at an interface between the charge storage layerand the gate; a tunnel dielectric layer formed at an interface betweenthe charge storage layer and the active regions; first and secondsource/drain regions formed at an exposed portion out of both sides ofthe gate in the active regions; and first and second bit lines connectedto the first and second source/drain regions respectively, and formed toextend in a bit line direction crossing the word line direction.

According to another aspect, the invention is directed to a method offabricating a non-volatile memory for 2-bit operation comprising:sequentially forming a tunnel dielectric layer, a charge storage layer,and a charge blocking layer on a semiconductor substrate; forming a hardmask for an isolation region defining active regions with a first zigzagpattern extending in a word line direction on the charge blocking layer,and partially being bent repeatedly; sequentially patterning the tunneldielectric layer, the charge storage layer, and the charge blockinglayer, using the hard mask as an etch mask; forming the isolation regionin the semiconductor substrate exposed to the hard mask; selectivelyremoving the hard mask; forming gates in a second zigzag pattern on thepatterned charge blocking layer to extend in a word line direction onthe semiconductor substrate, and partially to cross with the activeregions repeatedly and repeatedly to be bent in symmetry with the firstzigzag pattern; selectively removing the underneath exposed andremaining charge blocking layer, the charge storage layer and the tunneldielectric layer using the gate as an etch mask, thereby patterning suchthat the charge storage layer is confined to the portions where the gateand the active cross; forming first and second source/drain regions inthe active region at a region exposed out of both sides of the gate;forming an insulating layer to cover the first and second source/drainregions and the gate; forming a connecting contact penetrating theinsulating layer and exposing the first and second source/drain regions;and forming first and second bit lines on the insulating layer to beconnected to the first and second source/drain regions respectivelythrough the connecting contact and extend in a bit line directioncrossing the word line direction.

According to another aspect, the invention is directed to a method offabricating a non-volatile memory device for 2-bit operation comprising:sequentially forming a tunnel dielectric layer, a charge storage layer,and a charge blocking layer on a semiconductor substrate; forming a hardmask for an isolation region defining active regions defined as a zigzagpattern extending in a word line direction on the charge blocking layerand partially being bent repeatedly; sequentially patterning the tunneldielectric layer, the charge storage layer, and the charge blockinglayer using the hard mask as an etch mask; forming the isolation regionon the semiconductor substrate portion exposed to the hard mask;selectively removing the hard mask; forming gates of a straight patternextending in a word line direction on the patterned charge blockinglayer and partially crossing with the active regions repeatedly;selectively removing the underneath remaining charge blocking layer, thecharge storage layer, and the tunnel dielectric layer portion using thegate as an etch mask, thereby patterning to confine the charge storagelayer at a portion where the gate and the active regions cross; formingfirst and second source/drain regions at a portion exposed out of bothsides of the gate in the active; forming an insulating layer coveringthe first and second source/drain regions and the gate; forming aconnecting contact penetrating the insulating layer and exposing thefirst and second source/drain regions; and forming first and second bitlines on the insulating layer to be connected to the first and secondsource/drain regions respectively through the connecting contact andextend in a bit line direction crossing with the word line direction.

According to another aspect, the invention is directed to a method offabricating a non-volatile memory device for 2-bit operation comprising:sequentially forming a tunnel dielectric layer, a charge storage layer,and a charge blocking layer on a semiconductor substrate; forming a hardmask for an isolation region defining active regions defined as astraight pattern extending in a word line direction on the chargeblocking layer; sequentially patterning the tunnel dielectric layer, thecharge storage layer, and the charge blocking layer using the hard maskas an etch mask; forming the isolation region on the semiconductorsubstrate portion exposed to the hard mask; selectively removing thehard mask; forming gates of a zigzag pattern extending in a word linedirection on the patterned charge blocking layer, partially crossingwith the active regions repeatedly, and partially being bent repeatedly;selectively removing the underneath remaining charge blocking layer, thecharge storage layer, and the tunnel dielectric layer portion using thegate as an etch mask, thereby patterning to confine the charge storagelayer at a portion where the gate and the active regions cross; formingfirst and second source/drain regions at a portion exposed out of bothsides of the gate in the active regions; forming an insulating layercovering the first and second source/drain regions and the gate; forminga connecting contact penetrating the insulating layer and exposing thefirst and second source/drain regions; and forming first and second bitlines on the insulating layer to be connected to the first and secondsource/drain regions respectively through the connecting contact andextend in a bit line direction crossing with the word line direction.

The active region may be formed in a zigzag pattern to extend in theword line direction in the semiconductor substrate and partially to bebent repeatedly, and the gate may be formed in a straight pattern toextend in the word line direction on the semiconductor substrate, andpartially cross with the active region repeatedly.

Alternatively, the active region may be formed in a straight pattern toextend in the word line direction in the semiconductor substrate, andthe gate may be formed in a zigzag pattern to extend in the word linedirection on the semiconductor substrate, partially cross with theactive region repeatedly, and to be bent repeatedly.

The charge storage layer may be formed as a pair separated below thegate adjacent to the first and second source/drain regions adjacent toboth sides of the gate, and the gate extends to the active portionbetween separated two charge storage layers. The non-volatile memorydevice may further comprise a gate dielectric layer formed at aninterface between the gate portion extending between the two chargestorage layers and the active portion.

The charge blocking layer may extend to an interface between the gateportion extending between the two charge storage layers to coversidewalls of the charge storage layer and form the gate dielectric layerand the active portion.

The charge storage layer may be formed as a pair separated below thegate adjacent to the first and second source/drain regions adjacent toboth sides of the gate.

The gate may further include a first gate formed on the active portionbetween separated two charge storage layers; second gates aligned to thecharge storage layers on the two charge storage layers respectively, andattached to sides of the first gate; and a gate dielectric layer formedat an interface between the first gate portion and the active portion.

The gate dielectric layer may cover sides of the two charge storagelayers and may extend to an interface between the first gate and thesecond gate.

The charge storage layer may include a silicon nitride layer, apolysilicon layer, a layer of silicon dots, a silicon germanium layer,or nano crystal for charge storages.

The non-volatile memory device may further include an insulating spacerattached to sides of the gate, and a connecting contact in an SAC shapeconnecting the first and second bit lines and the first and secondsource/drain regions respectively.

The non-volatile memory device may further include first pads connectedto ends of the gates, and electrically connecting the word lines alignedtogether to outside; and second pads aligned separated from thealignment of the first pads, and electrically connecting the bit linesto outside.

Forming a gate may include forming a sacrificial layer on the chargeblocking layer as a mold following a shape of the gate and having anopening having a smaller line width than that of the gate; selectivelyremoving the exposed charge blocking layer, the charge storage layer,and the tunnel dielectric layer using the sacrificial layer as an etchmask, thereby exposing the underneath active portion and the isolationregion portion; forming a gate dielectric layer on the exposed activeportion to extend to sidewalls of the sacrificial layer; forming a firstgate on the gate dielectric layer to fill the opening; selectivelyremoving the sacrificial layer pattern; and forming a second gate in aspacer shape attached to sidewalls of the first gate, thereby formingthe gate.

Alternatively, forming a gate may include forming a sacrificial layer onthe charge blocking layer as a mold following a shape of the gate andhaving an opening with a line width equal to that of the gate; attachinga sacrificial spacer on sidewalls of the opening; selectively removingthe exposed charge blocking layer, the charge storage layer, and thetunnel dielectric layer portion, using the sacrificial layer and thesacrificial spacer as etch masks, thereby exposing the underneath activeportion and the isolation region portion; selectively removing thesacrificial spacer; selectively removing the remained charge blockinglayer portion exposed to the sacrificial layer, thereby exposing theunderneath remained charge storage layer portion; forming a gatedielectric layer on the exposed active portion to cover the exposedcharge storage layer portion and extend to sidewalls of the sacrificiallayer; forming a gate on the gate dielectric layer to fill the opening;and selectively removing the sacrificial layer pattern.

The gate may be formed to include a conductive polysilicon layer, asilicide layer, or a metal layer.

According to the present invention, there are provided a non-volatilememory device including arrays of a word line, a first bit line, asecond bit line, and an active region to operate non-volatile memorycells for 2-bit operation, and a method of fabricating the same.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing and other objects, features and advantages of theinvention will be apparent from the more particular description ofpreferred aspects of the invention, as illustrated in the accompanyingdrawings in which like reference characters refer to the same partsthroughout the different views. The drawings are not necessarily toscale, emphasis instead being placed upon illustrating the principles ofthe invention. In the drawings, the thickness of layers and regions areexaggerated for clarity.

FIG. 1 is a sectional view schematically illustrating a conventionalnon-volatile memory transistor device.

FIGS. 2 through 7 are plan views schematically illustrating a cell arrayof a non-volatile memory device for 2-bit operation according to a firstembodiment of the present invention.

FIGS. 8 through 17 are sectional views schematically illustrating anon-volatile memory device for 2-bit operation and a method offabricating the same according to a second embodiment of the presentinvention.

FIGS. 18 through 24 are plan views schematically illustrating anon-volatile memory device for 2-bit operation and a method offabricating the same according to a second embodiment of the presentinvention.

FIGS. 25 through 31 are sectional views schematically illustrating anon-volatile memory device for 2-bit operation and a method offabricating the same according to a third embodiment of the presentinvention.

FIGS. 32 through 37 are plan views schematically illustrating anon-volatile memory device for 2-bit operation and a method offabricating the same according to a third embodiment of the presentinvention.

FIGS. 38 and 39 are plan views schematically illustrating a cell arrayof a non-volatile memory device for 2-bit operation according to afourth embodiment of the present invention.

FIGS. 40 through 42 are plan views schematically illustrating a cellarray of a non-volatile memory device for 2-bit operation according to afifth embodiment of the present invention.

FIGS. 43 through 45 are views schematically illustrating aphotolithography process for realizing a zigzag pattern according to anembodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

The present invention will now be described more fully hereinafter withreference to the accompanying drawings, in which preferred embodimentsof the invention are shown. It should be noted that, throughout thedescription, unless noted otherwise, when a layer is described as beingformed on another layer or on a substrate, the layer may be formeddirectly on the other layer or on the substrate, or one or more layersmay be interposed between the layer and the other layer or thesubstrate.

In embodiments of the present invention, a memory cell array isprovided, in which a word line WL, a first bit line BL1 and a second bitline BL2 are independently connected to a non-volatile memory cell for2-bit operation. Each memory cell is structured to include onetransistor, and the transistor may be formed to include a gate, firstand second source/drain regions, and local charge storage layers.

The first and second source/drain regions are disposed opposite to eachother below the gate with a channel between them, and the local chargestorage layers are separated from each other, below the gate adjacent tothe first and second source/drain regions, respectively.

Continuously-aligned plural memory cells which are arrayed in the samedirection as regions in the semiconductor substrate to form a transistorstructure, for example, active regions extend are formed to be connectedto one WL, and plural WLs are aligned in parallel with the one WL. Theactive region may be formed in a direction in which the WL runs, thatis, extending in a WL direction, and some portions of the active regionare formed to be exposed out of the WL such that the WL and the activeregion partially overlap.

For example, either one of the word line WL and the active region may beformed with a zigzag pattern. Thus, the word line is partially in acrosswith the active region, and the crossed regions are repeatedly formedalong the direction that the active region extends, that is, the WLdirection, with bent portions of the zigzag pattern repeated. One memorycell is formed in the crossed region. Further, connecting contacts forthe connection of memory cells with the two bit lines BL1, BL2 areconnected to portions of an active region exposed to a region where theWL and the active region cross.

The WL and the active region may be all formed in zigzag pattern, and inthis case, the first zigzag pattern of the active region and the secondzigzag pattern for the WL may overlap such that portions of the activeregion in the region where the WL and the active region crossrepeatedly, or between crossed regions, are not partially hidden andexposed beside the WL.

For example, a first zigzag pattern of the active region may be a zigzagpattern bent in a right handed direction, and the WL may be a zigzagpattern bent in a left handed direction. That is, the first and secondzigzag pattern may be substantially in symmetry with each other. If thefirst and second zigzag patterns are disposed to overlap in plane, thefirst and second zigzag patterns are formed such that the partiallycrossed portion and the portion underneath the first zigzag pattern isexposed without crossed are repeatedly disposed.

The BL1 and BL2 may be formed to cross with the WL. The BL1 and BL2 areconnected to one memory cell, and a plurality of memory cells arerepeatedly disposed to cross with one WL repeatedly. The BL1 and BL2 arerespectively connected to the active region exposed to both sides of theWL through the connecting contact. Thus, connection contacts arerespectively formed to the active regions exposed to both sides wherethe active region and the WL cross with each other, and BL1 and BL2 areconnected to the connecting contacts respectively.

A physically separated local charge storage layer is formed at a crosspoint where the first zigzag pattern of the active region and the secondzigzag pattern of the WL are crossed. The charge storage layers areformed symmetrically below the WL adjacent to both sides of the WL,preferably, two charge storage layers are formed in one memory cell.Since the charge storage layers are formed physically separated, theycan be regarded as one locally separated charge node. Thus, whenconsidering one memory cell, two charge storage layers are formedrespectively in relation with discrete bit lines BL1, BL2.

The charge storage layers are formed only inside the region where theactive regions overlap. Thus, the charge storage layer does not extendover the isolation region determining the active region. Thus, a crosstalking phenomenon between the cells can be effectively suppressed.Thus, since the limitation of the device integration due to the crosstalking phenomenon can be eliminated, the integration of the devices canbe further increased.

FIGS. 2 through 7 are plan views schematically illustrating a cell arrayof a non-volatile memory device for 2-bit operation according to a firstembodiment of the present invention.

Referring to FIG. 2, the non-volatile memory device according to a firstembodiment of the present invention may include an active region 110formed in a first zigzag pattern shape. The active region 110, which isdefined by an isolation region 150, has a line shape extending along apredetermined direction, for example, a WL direction as shown in FIG. 2,and has bending portions 111 bent in the line at a predeterminedinterval so as to constitute a first zigzag pattern shape. The isolationregion 150 may include an insulating layer formed by a shallow trenchisolation (STI) method. Alternatively, the isolation region 150 may beformed using a local oxidation of silicon (LOCOS) process.

Referring to FIG. 3, the non-volatile memory device according to a firstembodiment of the present invention may include a gate pattern as a WL300 formed in a second zigzag pattern corresponding to the first zigzagpattern. The gate pattern, that is, the WL 300, has a line shapeextending along a predetermined direction, for example, a WL directionas shown in FIG. 3, and has bending portions 301 bent in the line at apredetermined interval so as to constitute the second zigzag pattern.

At this time, the second zigzag pattern of the WL 300 may be formed as azigzag pattern symmetric to the first zigzag pattern of the activeregion 110 (FIG. 2). For example, if the first zigzag pattern of theactive region 110 is a zigzag pattern bent in a right handed direction,the second zigzag pattern of the WL 300 may be a zigzag pattern bent ina left handed direction symmetric to the first zigzag pattern.

Referring to FIG. 4, the non-volatile memory device according to a firstembodiment of the present invention may be configured with an array, inwhich the second zigzag pattern of the WL 300 overlaps the first zigzagpattern of the active region 110. In this configuration, the secondzigzag pattern of the WL 300 is configured to partially cross with theactive region 110 of the first zigzag pattern, and crossing portions arerepeatedly provided along a word line direction.

Since the second zigzag pattern of the WL 300 and the first zigzagpattern of the active region 110 are formed in symmetry with each other,the crossing portions and portions of the active region 110 exposed outof both side ends of the WL 300 and not crossing with the WL 300 arerepeatedly provided along a word line direction. At this time, thesecond zigzag pattern of the WL 300 and the first zigzag pattern of theactive region 110 can be formed to cross with each other as shown inFIG. 4 such that the crossing portions between the second zigzag patternof the WL 300 and the first zigzag pattern of the active region 110 canbe preferably separated.

Referring to FIG. 5, the non-volatile memory device according to a firstembodiment of the present invention may include charge storage nodes orcharge storage layers 200, which are locally disposed only in each ofthe crossing portions of the active region 110 of the first zigzagpattern and the WL 300 of the second zigzag pattern, separated from eachother.

The non-volatile memory device, for example, asilicon-oxide-nitride-oxide-silicon (SONOS) device, has the chargestorage layer 200 as a node for capturing and storing charges disposedat an interface between the WL 300 and the active region 110. Thecharges captured in the charge storage layer 200 are used to change athreshold voltage V_(th) of the active region 110 below the WL 300, thatis, a channel, and to change a memory state of the transistor.

In the first embodiment of the present invention, the charge storagelayer 200 is locally formed only in a portion where the WL 300 and theactive region 110 cross. Thus, the charge storage layer 200 is notformed to extend below the WL 300 extending on an isolation region 150crossing the active region 110 and disposed adjacent to the activeregion 110.

Therefore, it can effectively suppress a crosstalking phenomenon betweenthe cells, which may occur when the charge storage layer extends on theisolation region. Therefore, the limitation of device integration due tothe crosstalking phenomenon can be eliminated, thereby furtherincreasing the integration of a device.

Two charge storage layers 200 are preferably disposed below the WL 300adjacent to both side ends of the WL 300 crossing the active region 110,in opposite to each other as shown in FIG. 5.

Referring to FIG. 6, the non-volatile memory device according to a firstembodiment of the present invention may be structured to include a bitline connecting contact 400, which contacts the portion exposed at bothside ends of the WL 300 of the active region 110. A portion to crosswith the WL 300 of the active region 110 is substantially used as achannel of the transistor of the memory cell, and portions exposed outof both side ends of the WL 300 of the active region 110 aresubstantially used as portions where source/drain regions of thetransistor will be formed.

For 2-bit operation in the transistor, bit lines BL are electricallyconnected to two source/drain regions of the transistor, respectively.The connecting contacts 400 of FIG. 6 are provided to electricallyconnect the source/drain regions of the transistor to the bit lines BL,respectively. Thus, the connecting contact 400 is formed to includeportions exposed out of both side ends of the WL 300 of the activeregion 110.

The connecting contact 400 may be formed as a self-aligned contact(SAC). That is, an insulation spacer is formed on the sides of the WL300, and the connecting contact 400 may be formed as an SAC to preventthe sides of the WL 300 from being exposed to a contact hole forconnecting contact by the insulation spacer.

Referring to FIG. 7, the non-volatile memory device according to a firstembodiment of the present invention may be structured to include bitlines 500 formed to cross with the WL 300. The bit lines 500 are formedsuch that two bit lines, for example, first and second bit lines BL1,BL2, 501, 503 are connected to one memory cell. The bit lines 500 may beformed in a line shape extending along a predetermined direction, forexample, a BL direction crossing with the WL direction.

With the WL 300 and the BL 500 aligned to cross with each other, wordline pads 630 for the WL 300 and bit line pads 650 for the BL 500 may berespectively aligned in different sides of the cell region where memorycells are aligned. For example, the word line pads 630 are aligned inthe region adjacent to a first side of the cell region, preferablyrectangular shape, and the bit line pads 650 are aligned in the regionadjacent to a second side of the cell region perpendicular to thealignment of the word line pads 630.

As such, since the cell alignment is made such that the WL 300 and theBL 500 cross with each other, the WL 300 and the BL 500 may be alignedin a matrix shape. Thus, specific memory cells among therepeatedly-aligned memory cells in a matrix shape can be selected by theselection of specific WL 300 and the selection of specific BL1 501and/or BL2 503. Thus, the word line pads 630 and the bit line pads 650may be aligned in different regions separated from each other as shownin FIG. 7. Thus, since the alignment of the pads 630, 650 in a coreregion and/or a peripheral region adjacent to the cell region may besignificantly simplified, complicated problems in the core region and/orthe peripheral region may not occur.

As such, a memory cell transistor is formed with the cell alignment ofthe non-volatile memory device according to a first embodiment of thepresent invention maintained.

FIGS. 8 through 17 are sectional views schematically illustrating anon-volatile memory device for 2-bit operation and a method offabricating the same according to a second embodiment of the presentinvention. FIGS. 18 through 24 are plan views schematically illustratinga non-volatile memory device for 2-bit operation and a method offabricating the same according to the second embodiment of the presentinvention.

Referring to FIGS. 8, 9 and 18, FIG. 8 is a sectional view taken alongline A-A′ of FIG. 18, and FIG. 9 is a sectional view taken along lineB-B′ of FIG. 18. As shown in FIG. 8, an isolation region 150 fordefining an active region 110 after an active layout as shown in FIG. 2is formed in a semiconductor substrate 100 such as a bulk silicon waferor silicon on insulator (SOI) wafer.

A layer for storing charges, that is, a charge storage layer 220, isformed on the semiconductor substrate 100. A first dielectric layer as atunnel dielectric layer 210 for tunneling of charges, particularly,electrons, is formed below the charge storage layer 220. The tunneldielectric layer 210 may be preferably formed to include a silicon oxidelayer.

The charge storage layer 220 is formed on the tunnel dielectric layer210. The charge storage layer 220 may be formed to include a materialbeing capable of capturing the electrons injected after tunneling, forexample, a silicon nitride layer. For example, as an oxide-nitride-oxide(ONO) structure, or an oxide-silicon-oxide (OSO) structure, a structureincluding the tunnel dielectric layer 210, the charge storage layer 220,and a charge blocking layer 230 can be provided. The charge storagelayer 220 may be composed of a material for storing charges such as aconductive polysilicon layer, a silicon dots layer, a silicon germanium(SiGe) layer, a nano crystal-aligned layer, and the like.

A charge blocking layer 230 for blocking back-tunneling during an eraseoperation of the non-volatile memory device may be formed on the chargestorage layer 220. For example, the charge blocking layer 230 may beformed to include a silicon oxide layer.

Then, a hard mask 155 for the isolation region 150 defining the activeregion 110 is formed on the charge blocking layer 230 as shown in FIG.8. The hard mask 155 may be preferably formed to include a siliconnitride layer.

Then, the tunnel dielectric layer 210, the charge storage layer 220, andthe charge blocking layer 230 are patterned, using the hard mask 155 asan etch mask, thereby exposing an underneath portion of thesemiconductor substrate 100. Since the hard mask 155 includes a patternshape for realizing the active region 110 of FIG. 2, the tunneldielectric layer 210, the charge storage layer 220, and the chargeblocking layer 230 are patterned in the same shape as that of the activeregion 110 (FIG. 2) as shown in FIG. 18.

Then, the exposed portion of the semiconductor substrate 100 is etchedusing the hard mask 155 as an etch mask, thereby forming a trench, andan insulating layer is formed to fill the trench, thereby forming theisolation layer 150. Also, the isolation process may be performed byforming a LOCOS isolation region on the exposed semiconductor substrate100 using the hard mask 155.

Then, the hard mask 155 is selectively removed, thereby forming anisolation region 150 for defining the active region 110 as shown inFIGS. 2 and 18, and concurrently forming a stack structure patternincluding the tunnel dielectric layer 210, the charge storage layer 220,and the charge blocking layer 230 as the same pattern as that of theactive region 110.

The charge storage layer 220 is formed to be confined inside the activeregion 110 (FIG. 2), and not to extend on the isolation region 150 bythe process. Thus, charges are confined inside the memory cell, that is,the active region 110, and charge spreading between cells and a mutualinterference phenomenon due to the charge spreading can be effectivelysuppressed or prevented.

Referring to FIGS. 10 and 19, a first sacrificial layer 710 is formed asa mold to form the WL on the charge blocking layer 230 of the stackstructure including the tunnel dielectric layer 210, the charge storagelayer 220, and the charge blocking layer 230 patterned along the shapeof the active region 110 or the outline. The first sacrificial layer 710is patterned in zigzag pattern shape as shown in FIG. 19, and the zigzagpattern is formed as a pattern for a second zigzag pattern shape of theWL 300 of FIG. 3.

For example, the first sacrificial layer 710 is patterned to have anopening 711 for a WL 300 as shown in FIG. 10. A line width of theopening 711 may be formed smaller than the line width of the WL 300 tobe formed. Thus, the opening 711 has a shape similar to the secondzigzag pattern of the WL 300 of FIG. 3 as shown in FIG. 19, but may beformed with a zigzag pattern having a relatively small line width.

Thus, the first sacrificial layer 710 may be formed as a zigzag patterncrossing the active region 110 (FIG. 2), and the opening 711 of thefirst sacrificial layer 710 is exposed by crossing a portion of thecharge blocking layer 230 as shown in FIG. 10. Further, the opening 711is formed such that the isolation region 150 adjacent to the pattern ofthe charge blocking layer 230 is exposed as shown in FIG. 19.

Referring to FIGS. 11 and 20, after the first sacrificial layer 710 isformed, an exposed portion of the charge blocking layer 230 isselectively etched, using the first sacrificial layer 710 as an etchmask. Exposed portions of the charge storage layer 220 and the tunneldielectric layer 210 are also selectively etched. Thus, the stackstructure pattern of the tunnel dielectric layer 210, the charge storagelayer 220, and the charge blocking layer 230, which are patterned toextend along the active region 110 as shown in FIG. 11, is separatedinto pieces, and a portion of the active region 110 of the underneathsemiconductor substrate 100 is exposed as shown in FIG. 20.

Referring to FIGS. 12 and 21, a second dielectric layer as a gatedielectric layer 810 is formed on the semiconductor substrate 100exposed to the opening 711 of the first sacrificial layer 710. The gatedielectric layer 810 is disposed at the interface between a subsequentgate and the active region 110 of the semiconductor substrate 100. Thegate dielectric layer 810 may be preferably formed to include a siliconoxide layer, and may extend to cover the sidewalls of the firstsacrificial layer 710.

Then, a first gate 310 is formed on the gate dielectric layer 810 tofill the opening 711 of the first sacrificial layer 710. The first gate310 may be used to constitute a portion of the WL 300 of FIG. 2. Sincethe first sacrificial layer 710 is formed in a zigzag pattern as shownin FIG. 21, and thus, the opening 711 is also formed in a zigzagpattern, the first gate 310 is also patterned in a zigzag pattern. Thezigzag pattern of the first gate 310 follows the pattern shape of thesecond zigzag pattern of the WL 300 of FIG. 2, but the line width of thefirst gate 310 may be narrower than that of the WL 300.

The first gate 310 may be formed to include a conductive material toconstitute a gate of the transistor, for example, conductivepolysilicon, a fully silicide layer, or a metal layer.

Referring to FIG. 13, after the first gate 310 is formed, the firstsacrificial layer 710 is selectively removed. Thus, the upper surface ofthe underneath charge blocking layer 230 covering the first sacrificiallayer 710, a portion of the active region 110, and a portion of theisolation region 150 are exposed.

Referring to FIG. 14, a second gate 330 exposed by the removal of thefirst sacrificial layer 710 is formed to be attached as a spacer shapeto the sidewalls of the gate dielectric layer 810. For example, after aconductive layer such as polysilicon, or a silicide layer, or a metallayer is formed, an overall etch such as a spacer etch is performed,thereby forming a spacer-shaped second gate 330. Thus, a gate 303including the first and second gates 310, 330 is formed in a secondzigzag pattern as the same pattern as that of the WL 300 as shown inFIG. 2.

Referring to FIGS. 15 and 22, a portion of the charge blocking layer 230exposed out of the both sides of the second gate 330 is etched andremoved, using the first gate 310 and the second gate 330 as etch masks,and the underneath charge storage layer 220 and the tunnel dielectriclayer 210 are etched and removed.

Thus, the charge storage layer pattern 223 is formed as a locallyseparated pattern as shown in FIG. 15. The charge storage layer pattern223 is isolated as a pattern confined only inside the active region 110like the charge storage layer 200 as shown in FIG. 5, and is patternednot to extend to the isolation region 150.

That is, the charge storage layer 220 is first patterned to be confinedinto the active region 110 during the process of forming the isolationregion 150 defining the active region 110 as shown in FIG. 18. Then, aportion of the charge storage layer 220 exposed by the second gate 330is etched and removed to be secondly patterned as shown in FIG. 15,thereby forming a charge storage layer pattern 223. Thus, the chargestorage layer pattern 223 is substantially confined and isolated insidethe active region 110 below the second gate 330. Thus, the two chargestorage layer patterns 223 are symmetrically formed on both sides of thefirst gate 310 separated from each other.

With the charge storage layer pattern 223 is formed, a charge blockinglayer pattern 233 and a tunnel dielectric layer pattern 213 on and belowthe charge storage layer pattern 223 are also patterned and formed aslocal patterns.

After the charge storage layer pattern 223 is formed, impurity ions areimplanted into an exposed region of the active region 110 adjacent tothe gate 303 using the gate 303 as an ion implantation mask, therebyforming a first impurity region 131. The first impurity region 131 maybe used to form the source/drain regions of the transistor as a lightlydoped drain structure. The active region 110 below the gate 303 betweenthe first impurity regions 131 is formed as a channel region 113.

Referring to FIGS. 16 and 23, a sidewall insulating spacer 410 is formedto cover and protect the sidewalls of the exposed second gate 330 andthe sidewalls of the charge storage layer pattern 223. The insulatingspacer 410 may be formed to include a silicon nitride layer and/or asilicon oxide layer.

Then, an ion implantation process is performed on the active region 110exposed by the insulating spacer 410, using the insulating spacer 410 asan ion implantation mask. Thus, source/drain regions 130 including thefirst and second impurity regions 131, 135 are formed. As shown in FIG.23, the source/drain regions 130 are formed as portions exposed by thegate 303 crossing the active region 110, that is, WL.

Referring to FIGS. 17 and 24, after an insulating layer 830 covering thegate 303 and the like is formed, a contact hole 831 penetrating theinsulating layer 830 and exposing the source/drain region 130 is formed.The contact hole 831 is formed during the process of forming an SACcontact, and may be formed to expose the sidewalls of the spacer 410 inorder to ensure a process margin. Then, a connecting contact 400connected to the bit line filling the contact hole 831 is formed toinclude a conductive layer. Since the connecting contact 400 is formedby the SAC formation process, the process margin can be further ensured.

Then, as shown in FIG. 24, a bit line 500 such as a BL1 501 and a BL2503 being connected to the connecting contact 400 is formed in the sameway as described in reference to FIG. 7. Since two BL 501, 503 areformed in across with one WL, that is, the gate 303, the memory cell mayoperate in 2-bit mode.

FIGS. 25 through 31 are sectional views schematically illustrating anon-volatile memory device for 2-bit operation and a method offabricating the same according to a third embodiment of the presentinvention, and FIGS. 32 through 37 are plan views schematicallyillustrating a non-volatile memory device for 2-bit operation and amethod of fabricating the same according to the third embodiment of thepresent invention.

The third embodiment of the present invention provides a process offorming a gate of a transistor and a structure by a different way fromthe second embodiment without a spacer-shaped second gate 330 (FIG. 17).

An isolation region 150 for defining an active region 110 following anactive layout as shown in FIG. 2 is formed on a semiconductor substrate100.

Referring to FIG. 25, a layer for charge storage, that is, a chargestorage layer 260 is formed on the semiconductor substrate 100, and afirst dielectric layer as a tunnel dielectric layer 250 is formed, and acharge blocking layer 270 is formed on the charge storage layer 260.

Then, a hard mask for an isolation region 150 defining the active region110 in the semiconductor substrate 100 as shown in FIG. 8 is formed onthe charge blocking layer 270. The tunnel dielectric layer 250, thecharge storage layer 260, and the charge blocking layer 270 arepatterned, using the hard mask as an etch mask, thereby exposing aportion of the underneath semiconductor substrate 100. Since the hardmask includes a pattern shape for realizing the active region 110 ofFIG. 2, the tunnel dielectric layer 250, the charge storage layer 260,and the charge blocking layer 270 are patterned in the same shape as theactive region 110 (FIG. 2) as shown in FIG. 18.

Then, an isolation region 150 (FIG. 18) is formed in the semiconductorsubstrate 100 exposed to the hard mask. Then, the hard mask isselectively removed, thereby forming the isolation region 150 definingthe active region 110 as shown in FIGS. 2 and 18, and concurrently,forming a stack structure including the tunnel dielectric layer 250, thecharge storage layer 260, and the charge blocking layer 270 in the samepattern as the active region 110 as shown in FIG. 25.

The charge storage layer 260 is confined inside the active region 110(FIG. 2) by the process, and does not extend to the isolation region150. Thus, charges are confined inside the memory cell, that is, theactive region 110, and charge spreading between cells and a mutualinterference phenomenon due to the charge spreading can be effectivelysuppressed or prevented.

Referring to FIGS. 25 and 32, a second sacrificial layer 730 is formedas a mold to form the WL on the charge blocking layer 270 of the stackstructure including the tunnel dielectric layer 250, the charge storagelayer 260, and the charge blocking layer 270 patterned along the shapeof the active region 110 or the outline. The second sacrificial layer730 is formed as a zigzag pattern for a second zigzag pattern shape ofthe WL 300 of FIG. 3.

For example, the second sacrificial layer 730 is patterned to have asecond opening 731 for the WL 300 as shown in FIG. 10. A line width ofthe second opening 731 may be formed with a line width equal to a linewidth of the WL 300 to be formed. Thus, the second opening 731 may beformed with the shape similar to the second zigzag pattern of the WL 300of FIG. 3.

Referring to FIGS. 26 and 33, after the second sacrificial layer 730 isformed, a sacrificial spacer 735 is formed on the inner sidewall of thesecond sacrificial layer 730. The sacrificial spacer 735 may be formedto include an insulating material, and substantially functions to reducea line width of the second opening 731. Therefore, an exposed portion ofthe underneath charge blocking layer 270 exposed to the second opening731 is relatively scaled down.

Using the second sacrificial layer 730 and the sacrificial spacer 735 asetch masks, the exposed portion of the charge blocking layer 270 isselectively etched, and thus, an exposed portion of the underneathcharge storage layer 260 and an exposed portion of the tunnel dielectriclayer 250 are also selectively etched. Thus, the stack structure patternof the tunnel dielectric layer 250, the charge storage layer 260, andthe charge blocking layer 270, which are patterned to extend along theactive region 110 as shown in FIG. 26, is separated into pieces, and aportion of the active region 110 of the underneath semiconductorsubstrate 100 is exposed as shown in FIG. 32.

Referring to FIG. 27, the sacrificial spacer 735 (FIG. 26) isselectively removed.

Referring to FIGS. 28 and 34, an exposed portion 271 of the chargeblocking layer 270 exposed by the removal of the sacrificial spacer 735is selectively removed using the second sacrificial layer 730 as an etchmask. Thus, a charge blocking layer dummy pattern 273 selectivelyexposing the underneath charge storage layer 260 is formed. Theprocesses may be optionally omitted in accordance with processing.

Referring to FIGS. 29 and 35, a second dielectric layer as a gatedielectric layer 820 is formed on the semiconductor substrate 100exposed to the second opening 731 of the second sacrificial layer 730.The gate dielectric layer 820 is disposed at the interface between asubsequent gate 350 and the active region 110 of the semiconductorsubstrate 100. The gate dielectric layer 820 may be preferably formed toinclude a silicon oxide layer, and may extend to cover the sidewall ofthe second sacrificial layer 730 and the exposed portion of the chargestorage layer 260. A portion 821 of the gate dielectric layer 820covering the charge storage layer 260 is substantially used as a chargeblocking layer.

Then, the gate 350 is formed on the gate dielectric layer 820 to fillthe second opening 731 of the second sacrificial layer 730. The gate 350may be used to constitute the WL 300 of FIG. 2. The second sacrificiallayer 730 is formed in a zigzag pattern as shown in FIG. 35, and thus,since the second opening 731 is also formed in a zigzag pattern, thegate 350 is also patterned in a zigzag pattern. The zigzag pattern ofthe gate 350 may be understood to follow the pattern shape of the secondzigzag pattern of the WL 300 of FIG. 2.

Referring to FIGS. 30 and 36, after the gate 350 is formed, the secondsacrificial layer 730 is selectively removed. Thus, an upper surface ofthe underneath charge blocking layer dummy pattern 273 covering thesecond sacrificial layer 730, a portion of the active region 110, and aportion of the isolation region 150 are exposed. Using the gate 350 asan etch mask, the portion of the charge blocking layer dummy pattern 273exposed out of the both sides of the gate 350 is etched and removed, andthen, a portion of the underneath charge storage layer 260 and a portionof the tunnel dielectric layer 250 are etched and removed.

Thus, the charge storage layer pattern 261 is formed as a locallyseparated pattern as shown in FIG. 30. The charge storage layer pattern261 is formed as a separated pattern confined only inside the activeregion 110 like the charge storage layer 200 as shown in FIG. 5, and ispatterned not to extend to the isolation region 150.

That is, the charge storage layer 260 is first patterned to be confinedinto the active region 110 during the process of forming the isolationregion 150 defining the active region 110. Then, the exposed portion ofthe charge storage layer 260 exposed by the gate 350 as shown in FIG. 30is etched and removed and secondly patterned, thereby forming a chargestorage layer pattern 261. Thus, the charge storage layer pattern 261 issubstantially isolated to be confined to a portion below the gate 350inside the active region 110, that is, below a charge storage layerportion 821 as an extending portion of the gate dielectric layer 820.Thus, two charge storage layer patterns 261 are symmetrically formed onboth sides below the gate 350 separated from each other.

With the charge storage layer pattern 261 patterned, the tunneldielectric layer pattern 251 below the charge storage layer pattern 261is also patterned, thereby forming a local pattern.

After the charge storage layer pattern 261 is formed as above, impurityions are implanted into an exposed region of the active region 110adjacent to the gate 350, using the gate 350 as an ion implantationmask, thereby forming a first impurity region 131. The first impurityregion 131 may be used to form the source/drain regions of thetransistor as an LDD structure. The active region 110 below the gate 350between the first impurity regions 131 is formed as a channel region113.

Referring to FIG. 31, a sidewall insulating spacer 430 is formed tocover and protect the sidewalls of the exposed gate 350 and thesidewalls of the exposed charge storage layer pattern 261. Then, an ionimplantation process is performed on the active region 110 exposed bythe insulating spacer 430, using the insulating spacer 430 as an ionimplantation mask, thereby forming a second impurity region 135. Thus,source/drain regions 130 including the first and second impurity ions131, 135 are formed.

Referring to FIG. 37, after an insulating layer covering the gate 35 isformed as FIG. 17, a contact hole penetrating the insulating layer andexposing the source/drain regions 130 is formed. At this time, aconnecting contact being connected to the bit line filling the contacthole is formed to include a conductive layer. Since the connectingcontact is formed by an SAC formation process, a process margin may befurther ensured.

Then, bit lines 500 such as BL1 501, BL2 502 being connected to theconnecting contact as shown in FIG. 24 are formed in the same ways asdescribed in connection with FIG. 7. Since two bit lines 501, 503 crosswith one WL, that is, gate 350, the memory cell performs 2-bitoperation.

FIGS. 38 and 39 are plan views schematically illustrating a cell arrayof a non-volatile memory device for 2-bit operation according to afourth embodiment of the present invention.

In the fourth embodiment unlike the first embodiment, a WL 300 (FIG. 2)may be formed in a straight pattern, not patterned in a second zigzagpattern. The processes of forming the transistor constituting memorycells in the fourth embodiment of the present invention may be performedin the same ways as described in connection with the second and thirdembodiments.

Referring to FIGS. 38 and 39, an active region 110 may be formed in azigzag pattern, and may extend to a WL direction. Further, a word line370 may be formed in a straight pattern to partially overlap the activeregion 110 such that a portion of the active region 110, for example, abending portion 111 of the zigzag pattern of the active region 110 isexposed. The bit line 500 including a first bit line 501 and a secondbit line 503 is formed to cross with the word line 370, and the BL 500may be aligned with the WL 300 in a matrix shape.

A connecting contact 400 may be formed in an SAC process as shown inFIG. 7 and as described in connection with the second and thirdembodiments.

In FIGS. 38 and 39, a charge storage layer 201 of two transistorsconnected to one connecting contact 400 connected to one bit line 500 isshown to extend through two transistors, but in the case that the chargestorage layer 201 is to capture charges, fix, and store the charges likean ONO, the two transistors can operate independently.

In this case, as described in connection with FIG. 5, the charge storagelayer 201 may be locally formed inside the active region 110 physicallyseparated from each other, by the same process as described inconnection with the second and third embodiments. Thus, since chargesare confined only inside the active region 110, charge spreading betweencells and a mutual interference phenomenon due to the charge spreadingcan be effectively suppressed or prevented.

Further, two neighboring transistors can be maintained separated in themiddle by changes of a line width or pitch of the active region 110 ofthe charge storage layer 201, a distance between the bending portions111, a line width of the word line 370, and the like.

FIGS. 40 through 42 are plan views schematically illustrating a cellarray of a non-volatile memory device for 2-bit operation according to afifth embodiment of the present invention.

In the fifth embodiment of the present invention, unlike the first andfourth embodiments, the WL 300 (FIG. 2) is patterned in a second zigzagpattern, and the active region may be formed in a relatively longstraight pattern. The processes of forming the memory cell in the fifthembodiment of the present invention may be performed in the same ways asdescribed in connection with the second and third embodiments.

Referring to FIGS. 40 through 42, an active region 190 may be formed ina straight pattern, and may extend in a WL direction. Further, a wordline 390 may be formed in a zigzag pattern partially overlapping theactive region 190 such that a portion of the active region 190repeatedly crosses or a portion of the active region 190 is repeatedlyexposed. The zigzag pattern of the WL 390 may be patterned substantiallyin the same shape as the second zigzag pattern shown in FIG. 2. A bitline 500 including a first bit line and a second bit line may be formedto cross with the word line 390, and the BL 500 may be aligned in amatrix shape with the WL 390 as shown in FIG. 42.

Referring to FIG. 41, a connecting contact 400 may be formed on theactive region 190 exposed to the WL 390, and may be formed as an SAC asshown in FIG. 7 or like the second and third embodiments.

Referring to FIGS. 40 and 42, a charge storage layer 203 (FIG. 40) oftwo transistors connected to one connecting contact 400 connected to onebit line 500 is formed to extend through two transistors, but in thecase that the charge storage layer 203 is to capture, fix, and storecharges like an ONO, two transistors may operate independently.

In this case, the charge storage layer 203 may be formed inside theactive region 190 separated from each other as shown in FIG. 5 and asdescribed in connection with the second and third embodiments. Thus,since charges are confined only inside the active region 190, chargespreading between cells and a mutual interference phenomenon due to thecharge spreading can be effectively suppressed or prevented.

Further, two neighboring transistors can be maintained separated in themiddle by changes of a line width or pitch of the active region 190 ofthe charge storage layer 203, a distance between the bending portions,and the like.

FIGS. 43 through 45 are views illustrating a simulation result todescribe a photolithography process for realizing a zigzag patternaccording to an embodiment of the present invention.

Referring to FIG. 43, the zigzag pattern for an active region or thezigzag pattern for a word line shown in the embodiments of the presentinvention may be realized to a real pattern by a photolithographyprocess using a mask pattern designed as shown in FIG. 43.

When the photolithography process performed using a mask patterndesigned as shown in FIG. 43 is examined through simulation, it isverified that the photoresist pattern of the zigzag pattern shown inFIG. 44 is realized. FIG. 45 shows results to verify that the activeregion and the gate are realized as zigzag patterns through simulation,and shows that the active region and the gate can be realized as zigzagpatterns.

The simulation results of FIGS. 44 and 45 were designed with a linewidth of 100 nm, an ArF light source for exposure, the number ofaperture (NA) of 0.85, and lens condition of 0.92-0.72 σ. An intensityof the light source during exposure is 55 mJ/cm².

The simulation results verify that the active region and/or the wordline can be realized in a zigzag pattern according to embodiments of thepresent invention.

The processes described in the description of the embodiments of thepresent invention exemplify methods of realizing structures for 2-bitoperation with physical separation. In the case of realizing atransistor employing one storage node, which is not separated, some ofthe processes are appropriately eliminated so as to realizenon-separated one storage node. In this case, a charge storage layerproviding a storage node is composed of a material for storing electronsby capturing and fixing electrons, for example, ONO, so as to provide2-bit operation.

Further, the transistors formed according to embodiments of the presentinvention may be structured in circuits as a flash memory device of NANDtype or NOR type.

According to the present invention as described above, a transistorconstituting a non-volatile memory device cell can induce a chargestorage layer or a storage node for storing charges to be confinedinside an active region. Since the charge storage layer is restrictednot to extend to an isolation region defining the active region,crosstalk between cells is prevented, and generation of charge spreadingand mutual interference phenomenon between cells is prevented.

Thus, integration of the non-volatile memory device can be furtherincreased since the integration limitation of the device due to themutual interference phenomenon of the charges between cells is overcome.

Further, since a cell transistor having a storage node with a physicallyseparated shape below one word line can be realized, a mutualinterference phenomenon between bits inside the cell can be suppressed.Thus, an advantage of the non-volatile memory device for 2-bit operationcan be realized.

Since a cell array is formed in a shape where a word line and a bit linecross, the word line and the bit line are aligned in a matrix shape.Thus, pads connected to the word line and/or the bit line are alignedwith divided in word lines only or in bit lines only. Thus, thealignment of pads in a core region and a peripheral region around a cellcan be further simplified, thereby solving complicated problems in thecore region and the peripheral region.

While the present invention has been particularly shown and describedwith reference to exemplary embodiments thereof, it will be understoodby those of ordinary skill in the art that various changes in form anddetails may be made therein without departing from the spirit and scopeof the present invention as defined by the following claims.

1. A method of fabricating a non-volatile memory for 2-bit operationcomprising: sequentially forming a tunnel dielectric layer, a chargestorage layer, and a charge blocking layer on a-semiconductor substrate;forming a hard mask for an isolation region defining active regionsextending in a word line direction on the charge blocking layer;sequentially patterning the tunnel dielectric layer, the charge storagelayer, and the charge blocking layer, using the hard mask as an etchmask; forming the isolation region in the semiconductor substrateexposed to the hard mask; selectively removing the hard mask; forminggates extending in the word line direction on the patterned chargeblocking layer, and partially crossing with the active regionsrepeatedly; selectively removing the underneath exposed and remainingcharge blocking layer, the charge storage layer and the tunneldielectric layer using the gate as an etch mask, thereby patterning suchthat the charge storage layer is confined to the portions where the gateand the active cross; forming first and second source/drain regions inthe active region at a region exposed out of both sides of the gate;forming an insulating layer to cover the first and second source/drainregions and the gate; forming a connecting contact penetrating theinsulating layer and exposing the first and second source/drain regions;and forming first and second bit lines on the insulating layer to beconnected to the first and second source/drain regions respectivelythrough the connecting contact and extend in a bit line directioncrossing the word line direction, wherein at least one of the gates andthe active regions are formed in a zigzag pattern.
 2. A method offabricating a non-volatile memory for 2-bit operation comprising:sequentially forming a tunnel dielectric layer, a charge storage layer,and a charge blocking layer on a semiconductor substrate; forming a hardmask for an isolation region defining active regions with a first zigzagpattern extending in a word line direction on the charge blocking layer,and partially being bent repeatedly; sequentially patterning the tunneldielectric layer, the charge storage layer, and the charge blockinglayer, using the hard mask as an etch mask; forming the isolation regionin the semiconductor substrate exposed to the hard mask; selectivelyremoving the hard mask; forming gates in a second zigzag pattern on thepatterned charge blocking layer to extend in a word line direction onthe semiconductor substrate, and partially to cross with the activeregions repeatedly and repeatedly to be bent in symmetry with the firstzigzag pattern; selectively removing the underneath exposed andremaining charge blocking layer, the charge storage layer and the tunneldielectric layer using the gate as an etch mask, thereby patterning suchthat the charge storage layer is confined to the portions where the gateand the active cross; forming first and second source/drain regions inthe active region at a region exposed out of both sides of the gate;forming an insulating layer to cover the first and second source/drainregions and the gate; forming a connecting contact penetrating theinsulating layer and exposing the first and second source/drain regions;and forming first and second bit lines on the insulating layer to beconnected to the first and second source/drain regions respectivelythrough the connecting contact and extend in a bit line directioncrossing the word line direction.
 3. The method according to claim 2,wherein the charge storage layer includes a silicon nitride layer, apolysilicon layer, a layer of silicon dots, a silicon germanium layer,or nano crystal for charge storages.
 4. The method according to claim 2,wherein forming a gate comprises: forming a sacrificial layer on thecharge blocking layer as a mold following a shape of the gate and havingan opening having a smaller line width than that of the gate;selectively removing the exposed charge blocking layer, the chargestorage layer, and the tunnel dielectric layer using the sacrificiallayer as an etch mask, thereby exposing the underneath active portionand the isolation region portion; forming a gate dielectric layer on theexposed active portion to extend to sidewalls of the sacrificial layer;forming a first gate on the gate dielectric layer to fill the opening;selectively removing the sacrificial layer pattern; and forming a secondgate in a spacer shape attached to sidewalls of the first gate, therebyforming the gate.
 5. The method according to claim 4, wherein theoperation of forming first and second source/drain regions comprises:performing an ion implantation on the active portion exposed by thesecond gate as an ion implantation mask, thereby forming a firstimpurity layer; forming an insulating spacer on sides of the secondgate; and performing an ion implantation on the active portion exposedby the insulating spacer as an ion implantation mask, thereby forming asecond impurity layer.
 6. The method according to claim 5, wherein theconnecting contact is formed as a self-aligned contact (SAC) shapecontacting the insulating spacer at sides.
 7. The method according toclaim 2, wherein the operation of forming a gate comprises: forming asacrificial layer on the charge blocking layer as a mold following ashape of the gate and having an opening with a line width equal to thatof the gate; attaching a sacrificial spacer on sidewalls of the opening;selectively removing the exposed charge blocking layer, the chargestorage layer, and the tunnel dielectric layer portion, using thesacrificial layer and the sacrificial spacer as etch masks, therebyexposing the underneath active portion and the isolation region portion;selectively removing the sacrificial spacer; selectively removing theremained charge blocking layer portion exposed to the sacrificial layer,thereby exposing the underneath remained charge storage layer portion;forming a gate dielectric layer on the exposed active portion to coverthe exposed charge storage layer portion and extend to sidewalls of thesacrificial layer; forming a gate on the gate dielectric layer to fillthe opening; and selectively removing the sacrificial layer pattern. 8.The method according to claim 7, wherein the operation of forming firstand second source/drain regions comprises: implanting ion impurities onthe exposed active portion using the gate as an ion implantation mask;forming an insulating spacer on sides of the gate; and implanting ionimpurities on the exposed active portion using the insulating spacer asan ion implantation mask, thereby forming a second impurity layer. 9.The method according to claim 2, wherein the gate is formed to includeat least one of a conductive polysilicon layer, a silicide layer, and ametal layer.
 10. A method of fabricating a non-volatile memory devicefor 2-bit operation comprising: sequentially forming a tunnel dielectriclayer, a charge storage layer, and a charge blocking layer on asemiconductor substrate; forming a hard mask for an isolation regiondefining active regions defined as a zigzag pattern extending in a wordline direction on the charge blocking layer and partially being bentrepeatedly; sequentially patterning the tunnel dielectric layer, thecharge storage layer, and the charge blocking layer using the hard maskas an etch mask; forming the isolation region on the semiconductorsubstrate portion exposed to the hard mask; selectively removing thehard mask; forming gates of a straight pattern extending in a word linedirection on the patterned charge blocking layer and partially crossingwith the active regions repeatedly; selectively removing the underneathremaining charge blocking layer, the charge storage layer, and thetunnel dielectric layer portion using the gate as an etch mask, therebypatterning to confine the charge storage layer at a portion where thegate and the active regions cross; forming first and second source/drainregions at a portion exposed out of both sides of the gate in theactive; forming an insulating layer covering the first and secondsource/drain regions and the gate; forming a connecting contactpenetrating the insulating layer and exposing the first and secondsource/drain regions; and forming first and second bit lines on theinsulating layer to be connected to the first and second source/drainregions respectively through the connecting contact and extend in a bitline direction crossing with the word line direction.
 11. The methodaccording to claim 10, wherein the forming a gate comprises: forming asacrificial layer on the charge blocking layer as a mold following ashape of the gate and having an opening with a smaller line width thanthat of the gate; selectively removing the exposed charge blockinglayer, the charge storage layer, and the tunnel dielectric layer portionusing the sacrificial layer as an etch mask, thereby exposing theunderneath active portion and the isolation region portion; forming agate dielectric layer extending to sidewalls of the sacrificial layer onthe exposed active portion; forming a first gate filling the opening onthe gate dielectric layer; selectively removing the sacrificial layerpattern; and forming a second gate as a spacer shape attached tosidewalls of the first gate, thereby forming the gate.
 12. The methodaccording to claim 10, wherein the forming a gate comprises: forming asacrificial layer on the charge blocking layer as a mold following ashape of the gate and having an opening with a line width equal to thatof the gate; attaching a sacrificial spacer to sidewalls of the opening;selectively removing the exposed charge blocking layer, the chargestorage layer, and the tunnel dielectric layer portion using thesacrificial layer and the sacrificial spacer as etch masks, therebyexposing the underneath active portion and the isolation region portion;selectively removing the sacrificial spacer; selectively removing theremaining charge blocking layer portion exposed to the sacrificiallayer, thereby exposing the underneath remaining charge storage layerportion; forming a gate dielectric layer on the exposed active portionto cover the exposed charge storage layer portion and extend tosidewalls of the sacrificial layer; forming the gate filling the openingon the gate dielectric layer; and selectively removing the sacrificiallayer pattern.
 13. A method of fabricating a non-volatile memory devicefor 2-bit operation comprising: sequentially forming a tunnel dielectriclayer, a charge storage layer, and a charge blocking layer on asemiconductor substrate; forming a hard mask for an isolation regiondefining active regions defined as a straight pattern extending in aword line direction on the charge blocking layer; sequentiallypatterning the tunnel dielectric layer, the charge storage layer, andthe charge blocking layer using the hard mask as an etch mask; formingthe isolation region on the semiconductor substrate portion exposed tothe hard mask; selectively removing the hard mask; forming gates of azigzag pattern extending in a word line direction on the patternedcharge blocking layer, partially crossing with the active regionsrepeatedly, and partially being bent repeatedly; selectively removingthe underneath remaining charge blocking layer, the charge storagelayer, and the tunnel dielectric layer portion using the gate as an etchmask, thereby patterning to confine the charge storage layer at aportion where the gate and the active regions cross; forming first andsecond source/drain regions at a portion exposed out of both sides ofthe gate in the active regions; forming an insulating layer covering thefirst and second source/drain regions and the gate; forming a connectingcontact penetrating the insulating layer and exposing the first andsecond source/drain regions; and forming first and second bit lines onthe insulating layer to be connected to the first and secondsource/drain regions respectively through the connecting contact andextend in a bit line direction crossing with the word line direction.14. The method according to claim 13, wherein forming a gate comprises:forming a sacrificial layer on the charge blocking layer as a moldfollowing a shape of the gate and having an opening with a smaller linewidth than that of the gate; selectively removing the exposed chargeblocking layer, the charge storage layer, and the tunnel dielectriclayer portion using the sacrificial layer as an etch mask, therebyexposing the underneath active portion and the isolation region portion;forming a gate dielectric layer extending to sidewalls of thesacrificial layer on the exposed active portion; forming a first gatefilling the opening on the gate dielectric layer; selectively removingthe sacrificial layer pattern; and forming a second gate as a spacershape attached to sidewalls of the first gate, thereby forming the gate.15. The method according to claim 13, wherein forming a gate comprises:forming a sacrificial layer on the charge blocking layer as a moldfollowing a shape of the gate and having an opening with a line widthequal to that of the gate; attaching a sacrificial spacer on sidewallsof the opening; selectively removing the exposed charge blocking layer,the charge storage layer, and the tunnel dielectric layer portion, usingthe sacrificial layer and the sacrificial spacer as etch masks, therebyexposing the underneath active portion and the isolation region portion;selectively removing the sacrificial spacer; selectively removing theremaining charge blocking layer portion exposed to the sacrificiallayer, thereby exposing the underneath remaining charge storage layerportion; forming a gate dielectric layer on the exposed active portionto cover the exposed charge storage layer portion and extend tosidewalls of the sacrificial layer; forming a gate on the gatedielectric layer to fill the opening; and selectively removing thesacrificial layer pattern.